The invention relates to a semiconductor device comprising a semiconductor body provided at a surface with a protection against damage caused by electrostatic discharge, which semiconductor body includes an island-shaped n-type surface region adjoining said surface, wherein a vertical npn-transistor is formed comprising an emitter, a base and a collector, which emitter is connected to a node to which, during operation, a reference voltage, for example ground, is applied, and the collector is connected to a bonding surface, and a diode having a breakdown voltage which is lower than that of the base-collector transition being arranged between the collector and the base.
Such a semiconductor device is disclosed, inter alia, in the patent document U.S. Pat. No. 5,341,005.
As the dimensions of integrated circuits decrease continuously and hence the circuit becomes more vulnerable to external influences, it becomes more important to design integrated circuits so as to be provided with an efficient protection against damage caused by electrostatic discharge (ESD), which is brought about, for example, by contact between a human body and an external contact pin connected to the circuit via a supply wire and a bonding pad present on the semiconductor body. The protection comprises an element which, under normal operating conditions is non-conducting or at least substantially non-conducting, so that it has no, or hardly any, effect on the operation of the circuit, and, when the voltage on the bonding pad exceeds a certain limit, this element becomes highly conducting enabling it to dissipate electric discharge current to, for example, ground.
The ESD protection described in the above-mentioned patent document U.S. Pat. No. 5,341,005 comprises a vertical bipolar npn-transistor whose collector is connected to the bonding pad and whose emitter is connected to ground. Between the collector and the, electrically floating, base of the transistor, a Zener diode is arranged to trigger the bipolar transistor. At a high voltage on the bonding pad, the Zener supplies current to the base, causing the transistor to become conducting and dissipate the electric charge to ground. In a special embodiment, an additional emitter is provided in the base, which emitter and the Zener jointly form a lateral npn-transistor. Said lateral transistor brings about a reduction of the breakdown voltage, while, in addition, the lateral transistor causes the on-resistance and the on-state voltages of the protection to be reduced. Since, however, in a lateral npn-transistor only a relatively small part of the pn-junction injects electrons into the base, the current carrying capability of this transistor is small and hence it contributes only relatively little to the current carrying capability of the protection. This is important because too high on-resistance and on-state voltages of the protection during ESD may cause the quality of the element to deteriorate. For this reason, the protection must be designed so as to be sufficiently large, and hence it takes up relatively much surface area of the circuit. An increase of the current carrying capability will therefore lead to a more robust element and/or to a protection having a smaller surface area. In addition, in the known ESD protection, a negative voltage on the bonding pad will cause the Zener to be forward biased and inject electrons which must be dissipated via the p-substrate, which may lead to latch up.
It is an object of the invention to provide, inter alia, an ESD protection which is compatible with standard IC processes and which has a large current carrying capability at a low on-state voltage, without an increase of the necessary surface area. The invention further aims at providing such an ESD protection wherein the risk that a negative voltage on the bonding pad will lead to latch up is much smaller than in the known device.
To achieve this, a semiconductor device of the type described in the opening paragraph is characterized in accordance with the invention in that the emitter is provided with an emitter contact which is also connected to the base, and in that, between the npn-transistor, hereinafter referred to as first transistor, and the diode, a second vertical npn-transistor is formed whose base is connected to the base of the first transistor, and whose emitter is conductively connected to the base of the second transistor. It is to be noted that the connection between the emitter zones and the associated base zones is to be taken to mean not only a short-circuit between the emitter and the base but also embodiments wherein the zones are interconnected via a resistor. As will be explained in greater detail by means of an example, in this construction, the second transistor, hereinafter also referred to as drive transistor, can send emitter current into the base of the first transistor, thereby contributing substantially to the current carrying capability of the protection. This also enables a reduction of the on-state voltage to be realized. Since the base is not electrically floating but connected to ground, possibly via a resistor, it is possible, in the case of a negative voltage on the bonding pad, to dissipate a large part of the electrons injected by the diode via the emitter and base connection instead of via the substrate, thereby substantially reducing the risk of latch-up.
A preferred embodiment of a device in accordance with the invention is characterized in that the emitter contact of the first transistor is connected to the base at a distance from the emitter. As a result of the distance between the emitter and base connections, a resistance is obtained which has a favorable effect on the operation of the transistor. In a modification, the base and the emitter of the first transistor are interconnected by a poly-resistor. A further preferred embodiment of a device in accordance with the invention, having a comparable advantage for the drive transistor, is characterized in that the emitter and the base of the second transistor are interconnected by means of a contact which is connected to the emitter and, at a distance from the emitter, to the base. In another embodiment, the emitter and the base of the second resistor are interconnected by a poly-resistor. A compact embodiment of a device in accordance with the invention is characterized in that the first and the second transistor have a common base zone and a common collector.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.